Physical Model of Low-Temperature to Cryogenic Threshold Voltage in MOSFETs

Threshold-voltage bias-temperature instability in commercially-available SiC MOSFETs

Physics-Based Scalable Threshold-Voltage Model for Strained-Silicon MOSFETs

In this paper, an analytical threshold-voltage (Vt) model derived from Poisson equation for NMOS devices with a strained-silicon channel is described in terms of band, material, doping, and structure parameters and validated with Medici simulations. The model equations are derived based on bulk reference to preserve the symmetry of the model, and extended to short-channel devices based on previ...

Hot-carrier reliability of MOSFETs at room and cryogenic temperature

Threshold voltage instabilities of present SiC-power MOSFETs under positive bias temperature stress

We study the threshold voltage (Vth) instability of commercially available silicon carbide (SiC) power MOSFETs or prototypes from four different manufacturers under positive bias temperature stress (PBTS). A positive bias near Vth causes a threshold voltage shift of 0.7 mV per decade in time per nanometer oxide thickness in the temperature range between -50°C and 150°C. Recovery at +5 V after a...

Effect of gate dielectric on threshold voltage of Nanoscale MOSFETS

An integrated circuit (IC) dimensions continue to decrease, RC delay, crosstalk noise, and power dissipation of the interconnect structure become limiting factors for ultra-large-scale integration of integrated circuits. Modern microcircuits may have eight metal layers, each separated by only 0.1 micrometers. RC delays and cross talk rather than transistor speed are now the major performance li...